Electrical circuits requiring high power handling capability while operating at high frequencies, such as radio frequencies (500 MHz), S-band (3 GHz), and X-band (10 GHz), have in recent years become more prevalent. Because of the increase in high power, high frequency circuits, there has been a corresponding increase in demand for transistors which are capable of reliably operating at radio and microwave frequencies while still being capable of handling higher power loads.
To provide increased output power, transistors with larger gate peripheries have been developed. One technique for increasing the effective gate periphery of a transistor is to provide a plurality of transistor cells that are connected in parallel in a unit cell configuration. For example, a high power transistor may include a plurality of gate fingers that extend in parallel between respective elongated source and drain contacts, as illustrated in FIG. 1.
In particular, FIG. 1 illustrates a metal layout of a conventional semiconductor transistor device 10 that includes a gate pad 12 and a drain pad 32 on a semiconductor substrate 20. FIG. 1 is a plan view of the device (i.e., looking down at the device from above). As shown in FIG. 1, in the conventional semiconductor transistor device 10, the gate pad 12 is connected by a gate bus 14 to a plurality of parallel gate fingers 16 that are spaced apart from each other along a first direction (e.g., the Y-direction indicated in FIG. 1) and extend in a second direction (e.g., the X-direction indicated in FIG. 1). The drain pad 32 is connected to a plurality of drain contacts 36 via a drain bus 34. In addition, source contacts 26 may also be located on the semiconductor transistor device 10. Each gate finger 16 runs along the X-direction between a pair of adjacent source and drain contacts 26, 36. A unit cell of the semiconductor transistor device 10 is illustrated at box 40, and includes a gate finger 16 that extends between adjacent source and drain contacts 26, 36. The “gate length” refers to the distance of the gate metallization in the Y-direction, while the “gate width” is the distance by which the source and drain contacts 26, 36 overlap in the X-direction. That is, “width” of a gate finger 16 refers to the dimension of the gate finger 16 that extends in parallel to the adjacent source/drain contacts 26, 36 (the distance along the X-direction). The gate periphery of the device refers to the sum of the gate widths for each gate finger 16 of the semiconductor transistor device 10.
In addition to adding unit cells, the gate periphery of a multi-cell transistor device may be increased by making the gate fingers wider (i.e., longer in the X-direction). As the gate fingers of a device become wider, however, the high frequency performance of the device may be adversely impacted. In addition, making the gate fingers wider typically means that the gate fingers must handle increased current levels, which can cause electromigration of the gate finger metallization.